An ESL-Based Design flow for Hardware
Acceleration of the GZIP Compression Algorithm
By Chad Spackman President, CebaTech
Emerging technologies and the ever-present
demand for higher speeds and traffic volumes in the data storage and
networking industries represents a challenge and an opportunity for
both 3rd party IP providers and the ESL industry. Demand
for high-value IP that represents increasingly complex software functions
can be expected to grow along with hardware acceleration applications.
Enabled by shrinking silicon geometries,
an advanced generation of high performance hardware offload for applications
like compression/decompression, TCP/IP, packet filtering, IPSEC encryption/decryption,
ISCSI, etc. is entirely possible. However, existing hardware design
entry and verification methods represent a significant constraint on
realizing the full potential of silicon trends for data and storage
applications. Comparatively primitive and disjoint in execution,
the time and test burden that contemporary RTL-based design methods
impose on complex algorithms or large designs becomes prohibitive in
cases where high order function or very large scale is the goal.
The serious practical limits of RTL simulation testing can, at best,
result in market delaying errors. At worst, they fail altogether.
Although there is general acknowledgment
within the industry of the limits of RTL design for complex multi-function
systems, and of the need for dramatically different ESL-based approaches
to hardware design, industry debate on how best to address the issues
is ongoing and fueled as much by the failures of the past as the needs
of the present. Today's ESL flows are supplements to traditional
flows. All allow more abstract design entry and each has a particular
area of specialization. None are meant to completely replace RTL
design entry at a chip level or even attempt to address chip level verification.
And many contemporary ESL solutions fall short by not adequately eliminating
the bottlenecks within current design processes, or by introducing their
own inability to scale to accommodate larger designs. In
the end, systems developers must compromise among inadequate choices
for the task of creating end to end systems and are often left integrating
disparate pieces of IP never designed to work together. Constrained
by available tools, 3rd party IP providers are also limited
in what they can deliver.
The opportunities for hardware acceleration
of advanced storage and data networking algorithms include bounded segments
of protocols that are within reach of traditional hardware development
flows as well as large domains of advanced networking protocols that
cannot be implemented without an advanced ESL flow and design framework.
This latter represents perhaps the higher value IP opportunity, but
a truly comprehensive ESL development framework should be able to significantly
benefit both ends of the value spectrum. An ESL framework should provide
a homogeneous development environment for high quality and predictable
results while the ESL flow supports unlimited scale and is able to take
advantage of proven software embodiments and trusted downstream synthesis
flows. To bring distinct advantage in delivering quality product
in optimal time, the ESL language itself should leverage proven software
source that is available to the designer.
A real-world demonstration of what can
be achieved with just such an ESL framework and methodology is a hardware
implementation of the well-known lossless compression/decompression
algorithm, GZIP with a configurable AES encryption function for data-at-rest
storage applications. Each of these IP blocks, although challenging,
can be achieved with traditional RTL flows. However, the GZIP
compression algorithm is very complex internally, and delivering all
of the capability it represents increases the development time and risk
accordingly. Adding value through integration of AES further
increases the risk and the test burden for the development project.
The complexity of the GZIP algorithm
derives from its support of multiple compression modes using LZ77 and
Huffman encoding. Hash table management, fixed Huffman support,
the generation of dynamic Huffman tables, and throughputs above 2Gpbs
represent a progressive increase in operational complexity that translates
into similar complexity and additional burden for an RTL-based flow.
Integrating multiple modes of AES encryption specific to data-at-rest
applications offers tremendous value to the compression solution, but
adds integration complexity, and compounds the risk, with similar impact
on the simulation coverage necessary to insure quality. Using traditional
design methods would require several man years of effort to deliver
production quality, fully tested, synthesize-able RTL representing
the GZIP and AES IP blocks described.
With the advanced ESL flow described
above, development time from start to production quality RTL occurred
in 3 man months - one month for each of GZIP inflate, GZIP deflate,
and AES encryption. Tremendous project benefit was realized through
the use of existing source code, already proven in real-world operation,
as the starting point for the design. Where an RTL-based design
must include a test plan for ever-present corner cases (e.g., odd byte
alignments on input and output gzip flows and the data padding present
throughout the gzip processing chain), proven software, by definition,
has long since addressed all imaginable corner cases. Immediately reflected
through the ESL tool and into the compiled RTL, this "captured"
operational hardening reduces required test time and is a key benefit
of the ESL design flow.
Starting with robust open source code
for compression and encryption (gzip, zlib, Rijndael) and working within
an ESL framework which incorporates an ESL tool supporting ANSI C and
all its implied capabilities, enabled rapid creation of a fully functional
GZIP w/AES IP core. In addition the environment allowed
the integration of an existing advanced DMA technology previously designed
within the framework, as well as software driver development beginning
at project start rather than after hardware had been realized.
The entire solution is a fully integrated 2Gbps, compression/encryption,
offload processor, incorporating advanced scatter/gather DMA and software
drivers. 90% of the hardware verification was done through native
C compilation and execution of the C source rather than simulation of
the compiler's RTL.
As an interesting side note, the interim
benchmark within the project was time to first RTL for the most complex
portion of the design (gzip compression). Adaptation of the gzip
source for compilation to RTL occurred across 3 days. Although
the result was as expected for the original single threaded source,
i.e., well less than 2 Gbps, the result allowed for nearly instant sanity
checking and the immediate pursuit of architectural alternatives.
The methods applied in the creation of
this GZIP/AES solution represent a coalescence of many ESL concepts
that have not previously achieved practical success in the industry,
but that are in fact the natural outcome of a fully integrated environment
based upon a high level language,
In our GZIP/AES example we chose to compile
the C that represents those components to hardware. This island
of C code however, sits inside a much larger C code base consisting
of all the systems that make up a transport and data storage offload
engine, which we have not yet chosen to compile to hardware.
The ESL platform allows software driver
development whether or not any of the platform components have been
compiled to hardware. Thus the GZIP source can be compiled to RTL and
run in a simulator while the transport software and associated software
drivers drive the simulation.
In the end the platform and ESL flow
together unify many of the valid ESL approaches to hardware and software
development that have to date been applied in an ad hoc manner due to
the lack of a common high level language. The environment used
in this example above provides a powerful platform on which to develop,
design, verify, and even market, complex end to end data networking
and storage solutions.
Chad Spackman, President and Co-Founder
of CebaTech, Inc. is a veteran in the ASIC/semiconductor industry.
His experience includes large scale ASIC design focused on advanced
data communications protocols.
He began his career as Senior Engineer with Fischer & Porter, led
ASIC design for Connectware, Inc. and served as co-founder and President
of Sandgate Technologies. Mr. Spackman holds a Bachelor of Physics,
a Bachelor and a Master's degrees in Engineering from the University
of Pennsylvania and Penn State University, respectively.
He has co-authored five patents in the semiconductor field.
