Integrated Subsystem IP: Addressing the Challenges of SoC Convergence
By Cary Snyder Mentor Graphics Corporation
The consumer device market
is evolving at a record pace. There is incredible convergence between
handheld, automotive, and home electronic technologies. System design
engineers face a multitude of challenges when designing and developing
ICs, systems, or subsystems in their effort to unleash the next great
multi-functional device. This article discusses subsystem IP and how
it addresses the challenges design teams face today. The time
has come to re-evaluate IP design strategies and methodologies.
Complexity is the
Challenge
Many of the complex embedded
ICs used today create overly difficult design challenges that can easily
become obstacles to success. This can happen anywhere in the IC or system
design process. The historical progression of why this is happening
is quite simple: The shrinking of computing systems along with the addition
of thousands of functional blocks combined with software that has experienced
exponential growth in the number of interacting modules. Those somewhat
familiar with micro-miniaturization process cannot escape the fact that
what was once occupied many rooms of space with memory measured in "bytes"
now fits comfortably into a piece of silicon no bigger than the space
between these brackets [ ] - with memory measured in billions
of bytes.
So what does this mean to
the embedded system engineer? In a single word "complexity."
Of course unmanageable comes to mind as well. One would think
a 10,000-fold concentration of embedded systems and subsystems and a
corresponding performance increase would be something in which to marvel
and appreciate. Instead, this incredible technological advancement becomes
part of an IC designer's perplexing daily routine, a routine that continues
to overwhelm the best and brightest in the industry.
How do EDA companies or more
specifically, IP vendors go about solving this challenge? One answer
might lie in altering how silicon chips are created. Another angle might
be to look forward at the types of products that can use these chips
and understand how quickly a design must enter the market. One might
also examine what attributes are required to evolve easy-to-implement
enhancements for original equipment manufacturers (OEMs). It comes down
to a simple complexity/cost management issue. A chip or chipset with
an extraordinarily large amount of digital logic with megabytes of memory
operating in the smallest space possible means there are an awful lot
of things that could go wrong. This is without question, the biggest
challenge in the embedded product development cycle.
Embedded
System Design has its Own Set of Complexities
While designers hear about
the unrelenting growth in IC computational capacity, are they truly
paying attention to what this entails? To understand the enormity
of the complexities, it only makes sense to look at how embedded system
design has evolved.
First let's look at what's
happening in the embedded products market. There is incredible convergence.
The formerly precise and well-defined boundaries between market segments
have been blurred beyond recognition. iPhones play music and take
pictures. Cameras send files wirelessly in real time. At the push of
a button, a podcast can be disseminated around the world, enabled by
file- sharing protocols and industry-wide standards. All kinds of multifunctional,
multi-mode devices integrate functions that a short while ago were standalone
embedded processing systems in their own respective market segment.
Figure 1. Mobile, automotive,
and home market segment convergence.
Most of the convergence happens
in three markets: mobile, consumer, and automotive. These three markets
are represented in Figure 1 as seen in the middle of the convergence
circle. This circle rotates as key functional options serve and then
become part of a neighboring market segment. Consumers now demand that
certain new functions be incorporated into similar type products, which
pull product development along. One might guess this new convergence
circle started by popular PC-based use of MP3 files on CDs. The automotive
electronics manufacturer found they could create automotive stereo systems
that played MP3 formatted CDs, and technologies quickly exploded from
this clever adoption of one market's feature into another market.
For designers who've been
around for a while, the concept of "big iron" may sound familiar.
Big iron can be defined as large, expensive, ultra-fast computers and
everything that comes with these massive systems. The term is currently
applied to powerful computer server farms whose steel racks and insatiable
appetite for electricity invoke the "big iron" association.
What's interesting to note, the functionality we now hold in the palm
of our hand is the functional equivalent to a ton of big iron a few
years ago.
Why is it important to mention
the big iron concept? It helps understand exactly the kind of computational
density that exists inside a portable device today. The number of complex
SoCs that fit into a mere one-inch square of printed circuit board,
each with tens of millions of gates along with megabytes of memory and
firmware is simply phenomenal.
IP
Integration at the Subsystem Level
The never-ending increase
in complexity of embedded systems and how much can be packed into a
single IC is only part of the affliction confronting SoC designers.
The chip design and completed IC have to ramp quickly into high volume
production in order for it to be considered a successful SoC product.
IC manufacturers realize and will go through great pains to enable their
OEM customers to get to market quickly. The smarter ones realize the
importance of well-supported and subsystem-proven RTOS' and subsystem
middleware/ software components that are optimized for a specific hardware
subsystem.
Taking it to the next step
shows that system and subsystem level design processes can be just as
important as the SoC development itself, or just as much at fault if
production schedules are not met. All of this places greater demands
on the functional verification and integration process.
The following are just a
few issues IP design teams must face during the IP integration process:
-
The IC design process cannot be handled independently of the system,
software, or subsystem integration - getting the end-product to market
quickly is often seen as the most critical consideration in the design
process.
-
Successful embedded system and subsystem performance rely heavily on
rapid software integration in the form of RTOS, middleware, drivers,
and sometimes the application itself. There is also a certain dependency
on external software in an interacting system or subsystem so this too
becomes part of a hidden-cost minefield.
-
Increasingly complex and evolutionary adaptations of standard interface
protocols and specifications create unforeseen complexity and added
cost situations. Embedded system interoperability depends on the appropriate
interpretations of industry standards, and the specific standard's compliance
verification requirements, further compounding quality design practices.
-
Shrinking time-to-market factors decreases product development schedules
often without a corresponding increase in resources or budget, and this
can introduce additional risks by pressure to cut verification corners.
-
The exponential rise in the number and complexity of subsystems being
integrated into a single chip can greatly increase the chance of some
flaw slipping through the verification process. Using silicon-proven
IP subsystems lowers this risk.
Like most people, engineers
and managers will loose focus of the bigger picture when so many interwoven
processes are treated as one. A person's SATA disk drive subsystem,
or Ethernet port, or USB subsystem is thought to be simple and teams
should work only on configuration or integration. Flawless subsystem
operation does not happen by accident. It's part of a well-executed
implementation plan. The real cost of IP use and integration is how
well and how quickly it meets its design goals.
An Embedded
Subsystem Strategy Must Include IP
Integration
The complex IP integration
process has many hidden costs. The typical SoC design starts out just
fine when the design emphasis is on a superordinate embedded system
or subsystem. As a result, subordinate IP subsystems, which can be equally
complex subsystems on their own, are often neglected. The relationship
between an external superordinate subsystem (main CPU, MPU, or DSP)
and subordinate SoC subsystems in a single SoC is shown in Figure
2. Each subsystem typically has its own unique layers of software
and hardware components, and often there will be external system, or
associated device dependencies that need to be taken into full consideration.
Most SoC or ASIC design teams
fail to check and verify IP subsystems either by omission or from underestimating
the complexity of the task. Often, the real subsystem verification along
with the required software occurs after silicon tape out, and by this
time it's too late to adjust features, add options, or even fix bugs.
When subsystem development
is pushed to the end of the product design cycle the results are often
times deficient as there is insufficient time for successful subsystem
implementation or integration. Consequently, this adds to the hidden
cost associated with IP integration, jeopardizing the overall product
development process and time to market schedules.
The concept behind offering
a complete IP subsystem is to help design teams avoid costly pitfalls
associated with subsystem integration and these very complex subordinate
boxes. It also provides a means to reinforce the integration design
team with the expertise they need by providing a seamless software and
system integration process.
USB Subsystem IP from
Mentor Graphics
Today's complex IC designs
feature more gates, tighter constraints, and higher expectations, which
increases the need for a kind of design flexibility offered by a subsystem
IP that's been silicon proven hundreds of times.
If all required embedded
system and subsystem functions were fully software programmable, as
system integrators think they are, there would be less pressure on getting
the fixed silicon resources right the first time. A processor-based
design approach helps in allowing software or firmware changes but a
more ideal situation results from using pre-designed and pre-verified
subsystems as functional blocks in a SoC - as they are most likely
to have the desired functional characteristics and generate minimal
integration issues or problems. Putting the right and proven hardware
in place, together with using proven software IP, can help make the
SoC design and integration a simpler software-driven task capable of
meeting tight schedule requirements.
Created by Mentor Graphics,
the USB subsystem IP is the industry's first ever fully integrated USB
subsystem. This specific USB subsystem IP includes a USB-IF logo compliant,
Multi-Mode, USB MAC that supports USB 2.0 Embedded Host, Dual-Role,
On-the-Go (OTG), and Device functionality. It also incorporates a PHY
or physical layer USB 2.0 interface. The subsystem offers several Mentor
USB software options. One option is Mentor's micro-software component,
OS agnostic and optimized for tiny footprint embedded applications.
Another choice
is the full-featured USB
software based on the Nucleus RTOS. Nucleus RTOS is part of the embedded
software division at Mentor Graphics which provides RTOS and USB middleware
as separate components or together as a fully certified IP building
block.
When combined with the embedded
USB subsystem hardware, the software component can implement on demand
or execute other OEM-defined roles as an Embedded Host or USB peripheral
- or even a fully USB-compliant OTG Dual-Role device with automatic
hard-wired host to device switching capabilities that are a featured
part of OTG.
Growing
Demand for Subsystem IP
It's common knowledge that
the next-generation SoC will be characterized by hundreds of subsystem
elements working as one. The average cell phone will have dozens of
SoC-like chips, a very complex embedded device capable of some extraordinary
functions. Figure 3 illustrates the complex nature of SoC
chipsets used in common embedded devices today. As you can see, there
is a control processor and a vast array of proven IP subsystems on the
same chip. With this being the typical SoC usage or environment, it
isn't hard to visualize the distinct advantage in using packaged subsystem
IP - both software and hardware IP - from a single source, which
can finally put an end to the finger pointing.
Figure
3. The complex nature of SoC chipset subsystems.
The conceptual SoC chipset
concept in Figure 3 shows four ICs occupying a small area inside
a handset. The diagram provides an exemplary representation of a Qualcomm
multimedia platform handset chipset to show the many SoC subsystems
required in a mobile multimedia platform. The 30 some red boxes only
highlight identifiable subsystems based on common functional features
together with available bill of materials IC lists.
A single-source IP subsystem
simplifies and speeds up the design of complex embedded systems and
SoCs. USB subsystem IP from Mentor Graphics has helped facilitate this
success in a number of ways, some of which typically fall under one
or more of the following characteristics.
- Embedded Design Productivity
Subsystem IP comes in the
form of pre-verified and silicon-proven IP subsystems, often validated
as being compliant to a particular specification or standard.
- Increased Flexibility
A key characteristic of packaged
subsystem IP is the flexibility offered at the IC design, IC validation
and integration, and embedded system implementation stages with feature-set
design options in the hands of the OEM or the end-user.
- Hardware-Optimized
Software Development and Integration
Software and system developers
can quickly implement features or subsystem options by using standard,
well-known software development tools.
- Optimized Time-to-Market
Capabilities
A chip is often sold to OEMs
who in turn, integrate and productize a SoC or SoC chipset. Pre-packaged
subsystem IP is designed as a highly optimized modular subsystem, with
the right hardware foundation and flexible software capabilities ideally
suited for OEM use.
- Embedded System Design
Productivity
Most embedded products benefit
from multi-processor subsystem configurations and purpose-built IP blocks
implemented in hardware combined with a corresponding soft IP in the
form of optimized RTOS, middleware, and associated software drivers.
Conclusion
The use of a fully integrated
and verified USB subsystem IP extends significant advantages not only
to the embedded system and subsystem design community, but also to silicon
vendors, OEMs, and others involved in the development of embedded products.
Application areas and market segments that will experience significant
benefits from the use of integrated subsystem IP include industrial,
mobile, consumer, and automotive product groups as they are under the
greatest pressure to increase their OEM flexibly by simplifying and
expanding their interconnect and peripheral subsystem options. The rapid
convergence and interchangeability of devices across multiple consumer-oriented
market segments will only increase the demand for subsystem-proven IP
as users continue to demand more functionality in smaller and even tighter
consumer device products.
