Common Platform
Technology Alliance Provides New Model for IC
Manufacturing
By Walter Ng
Senior Director, Platform Alliances
Chartered Semiconductor Manufacturing
IBM, Chartered Semiconductor
Manufacturing Ltd. and Samsung Electronics have developed a new foundry
model for the semiconductor market that offers enhanced flexibility,
portability, capacity and resources, while accelerating the rate of
technological innovation. This new model enabled through the Common
Platform technology alliance between IBM, Chartered and Samsung, drives
the implementation of common process technology across all three companies'
manufacturing facilities, combining the strength of a vertically integrated
approach similar to an IDM, with the benefits of outsourcing services
ranging from design through packaging.
The Common Platform technology
alliance builds on joint technology development efforts that started
at the 90nm process node, and has extended to 65nm , 45nm and 32nm processes.
The joint development efforts also include Infineon Technologies AG,
Freescale Semiconductor and STMicroelectronics, contributing valuable
expertise and 'real-world' implementation environments to further
develop advanced technology that the Common Platform alliance provides
to clients.
Common Platform technology
offers unique advantages over traditional foundry models
Customer choice
and flexibility
Single design, multi-sourcing
amongst 3 partners
GDSII compatibility
Flexible business
and technical engagement models
Foundry and ASIC
Time-to-market
advantage
Accelerated production
ramps and yield learning
Reduced design variability
with shared platform DFM offering
Supply assurance
Unconstrained upside
capacity
Robust and leading-edge
design enablement
Proven libraries,
reference flows and IP
Fab Synchronization
The three manufacturing partners
that make up the Common Platform combine unique expertise and proven
strengths. Customers can utilize one or multiple partners for manufacturing
purposes that offer not only multiple fabs, but fabs that are geographically
diverse. Thus, semiconductor designs can be produced in different
fabs for different customers or regions, greatly reducing supply chain
costs in a global environment.
IBM, Chartered, and Samsung
invest heavily in processes synchronization using common test vehicles
at all three fabs to drive commonality between the sites. Common in
line electrical test specs and wafer acceptance criteria are needed
across all fabs. Critical parameters need to be monitored and tweaks
fed back to litho, OPC, data prep, metrology and masking making. Hardware
must be measured to ensure parameter equivalency. Common L1/L2 qualification
methods are used. Parametrically equivalent fabs allow single
GDSII designs to be manufactured at multiple sites without redesign.
Complex analog functionality may require additional characterization
and testing.
Just as the global diversity
of the manufacturing sites also mitigates risk, it also provides more
manufacturing and engineering support. With the fabs located in
Singapore, South Korea and the United States, multiple engineering teams
at multiple fabs can work to resolve issues and improve manufacturing
efficiency around the clock, rather than be limited as a single fab
and engineering team in the traditional foundry model.
With knowledge in different
products and application areas, each company in the Common Platform
technology alliance also offers a wide range of expertise and experience.
This knowledge and support can be critical during the ramp of a new
product. With three distinct companies joining together to coordinate
yield ramps, various resources have been cross-geographically leveraged.
Such resources include wafers and indigenous processes for yield learning
and engineering talent and have led to cost reductions and industry-leading
ramp times.
IP selection with Chip Estimate
The Common Platform technology
alliance is working with a robust ecosystem of design enablement partners
that provide consistent and reliable support for designs targeting any
of our manufacturing facilities. An important part of this support is
proven IP, and the alliance members are working with solutions providers
to offer a comprehensive digital and mixed-signal IP portfolio.
Now, in conjunction with
Chip Estimate, the Common Platform offers a unified portal to streamline
IP search. Electronics designers can go to one location at http://www.commonplatform.com/ipsearch
to find a complete catalog of 90nm, 65nm and 45nm IP that has been developed
and proven on Common Platform technology.
The Common Platform IP Portal streamlines access to comprehensive data
on semiconductor IP, including component features, deliverables, quality
and status in silicon, and connects designers directly to the respective
IP suppliers. The launch of the portal delivers on a goal of the Common
Platform technology alliance to foster a robust design enablement ecosystem
to benefit the electronics design industry.
The Common Platform IP portal is available immediately and is a free
service to the semiconductor design community. To search for IP and
learn more, please visit: http://www.commonplatform.com/ipsearch
Learn more about the Common
Platform at the Common Platform Tech Forum
The Common Platform technology alliance will host its first-ever Common Platform
Technology Forum on Tuesday, November 6, 2007 at the Santa Clara Convention
center in Santa Clara, California. Registration
for this informative event ends October 30 so act quickly to reserve
your place.
Based on the popular day-long
format that Chartered has presented for many years, this year's event
gives customers access to executives, technologists, roadmaps and strategies.
Attendees will hear first hand
how the power of collaboration amongst this group of industry leaders
can help develop leading-edge electronic products.
Highlights include:
Keynotes from Michel
Mayer of Freescale Semiconductor and Behrooz Abdi of QUALCOMM CDMA Technologies
In-depth technical
sessions on advanced technologies, DFM and material science
Roadmap presentations
detailing future directions for Common Platform technology
Solutions provider
pavilion featuring more than 30 enablement partners, including leading
EDA, IP, libraries and design services companies
Please register early as space
is limited. Detailed information about this important event
can be found at: http://www.commonplatform.com/tf2007/ and will be updated continuously.
About the Author
Walter Ng is responsible for identifying, developing and executing customer and partner alliances that advance the adoption of Chartered's solutions for the leading-edge and mainstream technology nodes. Walter has led the company's collaboration with IBM and Samsung to define the strategy and implementation for Common Platform™ design enablement platform at 90 nanometer (nm) and 65nm. Previously, Walter served as senior director of design solutions and was responsible for driving and managing Chartered's relationships with third-party EDA and IP partners. Walter has been in the electronic design and EDA industry for more than 18 years. Prior to joining Chartered, Walter was Director of Business Development and Asia Pacific Operations with Sequence Design. In this position, he was responsible for establishing, managing and growing Sequence Design's Asia Pacific sales channel and marketing activities in addition to managing the strategic relations program for foundries, EDA and IP partners. From 1994 to 1999, Walter worked with Cadence Design Systems, where he held positions in strategic marketing and numerous roles in applications engineering, consulting services, sales support and marketing. Previously, he has held various senior design and test engineering positions in Raytheon's Equipment Development Labs. Walter holds a B.S. in Electrical Engineering from the University of Massachusetts, Amherst, and an M.B.A from the University of Massachusetts, Boston.
