Solving the Integration Challenges
of USB-Enabled Designs
By Gervais Fong
Sr. Product Manager, DesignWare PHY IP
Synopsys
Today's IP choices
for the Universal Serial Bus (USB) cover many different types of interfaces
for a wide variety of applications-including portable consumer products.
Power consumption and small form factors are key issues. SoC designers
must also consider new requirements imposed by smaller technology nodes,
especially for the USB PHY. This article provides insights into dealing
with these issues and profiles the USB IP choices available from Synopsys.
As the most successful
connectivity standard in history, USB has expanded from connecting PCs
and PC peripherals to flash storage, digital imaging, audio and video,
wireless, automotive, and now to tremendous growth in mobile phones.
A force behind this growth are the ongoing enhancements to the USB standard,
including the PictBridge specification that supports direct connections
between printers and digital cameras and most recently, the Link Power
Management (LPM) and High Speed Inter-Chip (HSIC) standards that lower
power and enable chip-to-chip connectivity with USB.
Overview of USB Design
Issues
Today, issues such
as power consumption and small form factors in consumer products drive
many of the key USB challenges for the design community. While USB logo
compliance and interoperability are important for any application, they
are especially critical for consumer applications, where any compatibility
glitch leads to higher support costs and loss of market opportunity.
It is also important
to remember that USB is standardized, but the standard itself is not
an implementation specification. The IP must be designed and integrated
to maximize overall system performance. For example, with Hi-Speed USB
2.0, performance through the core must be maximized to achieve the interface's
full bandwidth. Otherwise, it might be necessary to use a microcontroller
to handle USB transactions.
Naturally, the PHY
must be available in the foundry of choice. Within the capabilities
of that foundry, the PHY must be designed to provide maximum performance
margin relative to the USB specification so that the design achieves
high yield and is cost effective. With chip ASPs less than a dollar
in some market segments, the ability to maximize chip yield with the
USB IP can mean the difference between product success and failure.
Fabrication
Issues
Shrinking process geometries
bring clear benefits to the digital portion of the USB interface, but
the shrink is less favorable for USB PHYs. Down to the 90 nm technology
node, 3.3V thick-oxide devices have been used for implementing analog
circuitry in the PHY. However, in 65 and 45 nm processes and even some
90 nm processes, the available thick-oxide device does not exceed 2.5V.
In fact, starting at 45 nm, some thick-oxide transistor process options
do not exceed 1.8V.
How do these transistor
options affect the PHY? Examining a cross section of a transistor makes
the issue clear. As devices shrink, the transistor's gate becomes
narrower. This decreasing gate width and the drain/source voltage issues
associated with a narrower channel make it difficult to sustain traditional
I/O voltages such as 3.3V.
More importantly, the
narrow gate allows electrons to pass from source to drain with little
interference - an effect referred to as hot carrier injection (HCI).
This effect tends to break down the depletion region between the source
and drain quickly if the voltage is too high. Voltages more than about
10 percent above the design voltage are usually too high.
The problem is that
the USB specification requires a 3.3V rail on the transmit (TX) and
receive (RX) lines. TX must signal a minimum VOH of 2.8V, and RX can
see a maximum VIH of 3.63V. Other signals (DP/DM and VBUS) can see signals
as large as 5.25V.
While it is possible
to overdrive the I/O with 2.5V thick-oxide devices to achieve the required
voltages, operating at these voltage levels without a properly designed
2.5V or 1.8V PHY can result in significant lifetime device degradation.
As a result, reliability problems and field failures will occur. Because
the USB PHY must be available at smaller technology nodes, it is essential
to have a USB PHY that is fully compliant with the USB 2.0 specification
while maintaining long-term reliability. The solution is to implement
a new USB PHY architecture that uses a triple-supply domain:
- 0.9 to 1.2V for
digital and low-voltage analog circuits
- 2.5V to supply
the analog circuitry
- 3.3V to supply
the USB PHY I/O that handles higher voltage levels
Synopsys developed
this new architecture and verified it with thousands of hours of reliability
simulations to ensure that none of the devices are overstressed. The
result is a USB PHY that meets the USB standard and complies with foundry
rules for long-term reliability. Additional benefits included lower
power consumption and smaller area due to greater use of 2.5V devices.
Synopsys' latest-generation USB 2.0 PHY family - the DesignWare
USB 2.0 nanoPHY-uses this approach and is available in 130 nm, 90
nm, 65 nm, and 45nm processes.
USB
"dis-integration"
Another way to deal
with the I/O voltage issue is to avoid it altogether by taking the PHY
out of the SoC containing the digital circuitry. The PHY can be implemented
in a separate chip that provides the appropriate voltages.
This "dis-integration"
option is also being used to solve another challenge - the increasing
expense of moving to smaller process geometries. In fact, this option
addresses a number of issues:
- Increasing numbers
of products require Hi-Speed USB
- Product development
schedules are shrinking
- USB PHY IP may
not always be available or proven in specific smaller-process geometries
- Shorter test time
with low pin count interface
- Companies may not
have the resources to integrate the controller and PHY into a single
leading-edge process- based chip.
In the "dis-integration"
approach, the USB controller is integrated with the digital logic on
a CMOS chip that is fabricated at 65 nm or smaller, while the PHY is
integrated with other analog circuitry on a separate chip fabricated
using a larger geometry process. For example, a separate power-management
chip is a good candidate for integrating the PHY. Whatever chips are
involved, they can be combined on a PCB or in a multichip module (MCM)
using die-to-die connections.
The "dis-integration"
approach relies upon a relatively new USB standard called the UTMI+
Low Pin Interface (ULPI) for connecting the USB controller and PHY.
While the industry-standard UTMI+ interface connects these functions
within a single chip, ULPI connects them across two different chips.
ULPI reduces the interface from approximately 40 - pins to 8 - 12 pins.
High
Speed Inter-Chip USB and Link Power Management
A new USB interface
- High Speed Inter-Chip USB (HSIC) - is providing the basis for
a different kind of "dis-integration" compared to the controller/PHY
separation described earlier. Rather than supporting the "dis-integration"
of USB itself, HSIC USB makes it easier to interconnect other functionality
that has been partitioned into multiple chips. This new standard leverages
the availability and knowledge of existing USB infrastructure to make
connections between chips on a PCB or inside a multichip module.
Aside from the "dis-integration"
concept, HSIC USB offers an easy way to connect many different types
of functions in a system. Since USB is already used extensively to connect
products using the traditional USB cable, it is a good choice to move
inside the system and act as a high speed chip to chip interface.
For example, HSIC USB can be used to connect an embedded webcam, GPS,
or Wifi chip to an applications processor within a smart phone or small
form- factor embedded PC. Significant time and cost is saved because
USB drivers and firmware that work with traditional USB 2.0 systems
can be reused in HSIC USB applications.
Supporting high-speed
data transfer rates, HSIC enables inter-chip connectivity by providing
USB PHY implementations while eliminating cables and the analog component
in the PHY. It operates at low-voltage CMOS levels and the interface
is quite simple-just two wires. It saves power and minimizes costs
by removing the need to support the traditional USB 2.0 Full Speed and
Low Speed protocols. HSIC will see initial designs in 2008.
The Link Power Management
(LPM) standard implements a new power sleep state to reduce power consumption.
The USB LPM IP can provide faster suspend and resume times by three
orders of magnitude (now microseconds instead of milliseconds) compared
to the existing USB 2.0 specification, allowing devices to save power
by more frequently turning off the USB connection while idle. Today, Synopsys provides a
comprehensive USB digital and PHY IP solution that supports the HSIC
and LPM standard.
The Power Challenge
One of the biggest
design challenges for USB and nearly all other IP is the need to reduce
power consumption. Battery-powered products constitute the fastest growing
segment of the USB 2.0 market. These applications demand low active
power, and more importantly, minimal standby (leakage) power. Many design
methods are available to reduce both active and leakage power, and Synopsys
has taken advantage of these methods to reduce the active power consumption
of the USB 2.0 nanoPHY to approximately half the power of traditional
USB 2.0 PHYs and bring leakage to an extremely low level.
A holistic approach
to low-power design reduces the power requirements for both the digital
and analog blocks of the PHY. Redesigning the core's PLL/DLL architecture
provided significant power reductions by eliminating the need for complex,
high-frequency clocking circuitry. A new transmit architecture further
reduces active power consumption. In the case of an implementation in
TSMC's 65LP process, for example, the DesignWare USB 2.0 nanoPHY consumes
much less than 75 mW during high-speed (HS) transmit mode and has a
minuscule leakage current of just 3 uA.
It is worth noting,
too, that the architectural changes greatly reduce the DesignWare USB
2.0 nanoPHY's area. to about half that of other current-generation
USB 2.0 PHY IP, depending on the technology used. Unlike other mixed-signal
designs, the DesignWare USB 2.0 nanoPHY's floorplan allows the digital
block to scale with smaller process geometries, so the overall macro
area shrinks, while still providing excellent performance. In addition,
the IP's tunability feature helps deal with variances brought about
by migration to smaller, less mature process geometries such as 65 and
45 nm which can lead to less than ideal PHY performance relative to
the USB specification.
Summary
As the leader in USB
IP for six years in a row (Dataquest 2007), Synopsys provides a broad
range of USB IP for both wired and wireless USB applications. Working
closely with major foundries, Synopsys delivers silicon-proven IP that
has excellent yield in high-volume production and provides many features
that simplify integration for low design-in cost. Designers have utilized
the complete portfolio of USB verification, digital controller, and
mixed-signal PHY IP cores to successfully produce over 300 USB enabled
designs that have shipped an estimated 500 million production units.
Figure 5: Synopsys DesignWare USB IP Complete
Solution
Gervais Fong is a Senior Product Manager for Mixed-Signal
PHY IP at Synopsys. Gervais has over 15 years of experience holding
product marketing and product management positions covering ASIC, FPGA,
EDA, and IP products. Gervais holds a Bachelor of Science degree in
Electrical Engineering and Computer Science from the University of California,
Berkeley.
