The Next Generation of DFM
Tools: Die-Level Parametric Variation Monitoring
By Ken Harris
Senior Technical Writer and Illustrator
Ridgetop Group
Designers and manufacturers
using sub-90 nm process geometries face adapting
to many challenges encountered in the nanoscale crossover. As
sizes shrink, statistical variations grow
wider and multivariate relationships expand in
number. The logic of the situation is both simple and remorseless. With
each process node, geometries shrink, new materials are added, masking
steps increase and become more intricate, and design rules ever trickier.
To compensate for the sub-wavelength lithography bottleneck, design
is more complex. As integrated circuit (IC) feature sizes reduce, manufacturing
processes become more complex. Process complexity creates new defects
while smaller features result in circuits more susceptible to electrical
faults. Defect detection must become
more sensitive to keep up with each process generation. In the crush
of the downward spiral, all of the slack in the system is eliminated.
So, just as the semiconductor industry
evolves to find the right balance, DFM has seen test, reliability, diagnostics,
random yield, and systematic yield incorporated under the DFM umbrella.
Parametric variation monitoring for yield optimization is the latest
generation of DFM tool and it is a greatly needed step in the right
direction. Properly designed DFM tools and libraries can help enable
"process-aware" design methods maintain high production
yields.
Designing For Yield (DFY)
Optimizing yield is a weathered cornerstone
of the semiconductor industry. The crossover into nanoscale fabrication
has made mastering yield even more intricate and complicated than ever.
One of those complications is a shift from process variation to parametric
variation as the dominant source of yield-limiting defects. This makes
the emergence of electrically-based DFM (E-DFM) tools critical for addressing
parametric yield failures.
In its 2007 Technology Roadmap, the
ITRS (International Technology Roadmap for Semiconductors) made parametric
variation a top challenge across the industry stating, "there is a
real business need to be able to isolate electrically to at least the
failing transistor or interconnect in the future, or suffer the economic
consequences of reduced yield improvement..."
Parametric Variation &
Yield Loss
Parametric-related yield losses are
caused by variations in electrical properties. This is in contrast to
process-related yield losses, which are caused by variations in the
physical properties such as doping profiles or oxide thicknesses. So,
DFM tools can be categorized as physically-based or electrically-based.
Designers want a realistic electrical measurement for critical parameters
such as threshold voltage matching that will drive circuit designs...not
process-driven measurements commonly used in older, scribe line approaches.
In the nanoscale CMOS processes currently
being developed and refined, parametric variation is associated with
systematic and random intra-die effects. The push into advanced technology
nodes has produced an unintended side effect. Placing more features
into smaller places creates a crowding issue with a dramatically negative
impact on yield and performance. At 90 nm and below, systematic defects
increase steadily at a faster rate than random defects as the source
of yield loss by technology node.
To illustrate this, within the category
of systematic yield defects, there are two major subcategories: 1) lithography
/ new materials-based and 2) design-based. At the 130 nm node, systematic
defects are roughly an equal split between the two subcategories. A
dramatic increase is obvious at the 90 nm node where the ratio is approximately
2.5 : 1 for design-based versus lithography / new materials yield defects.
The slope for design-based yield loss
is reminiscent of a bad airplane movie: at 350 nm businessmen are complaining
about service, at 250 nm the babies start crying, at 180 nm cue the
screaming, at 130 nm the crew start disappearing, and at 90 nm the pilots
have bailed leaving the passengers in hysterics and the businessmen
are still wondering where their drinks went. Welcome to business-class
in semiconductor manufacturing. The flashing sign at 90 nm indicates
a bumpy ride from here until Moore's Law cancels everyone's frequent
flier miles.
Figure 1: Defect Categories
by Yield and Process Nodes
There is good news - systematic yield loss can be mitigated, particularly
the design-related part that accounts for an estimated loss of $30B/year.
So now, the clarion call by ITRS for rapid development in all areas
of parametric monitoring, testing, yield loss / learning, and DFM tools
becomes apparent. NanoDFM or reducing yield loss and
optimizing performance through die-level parametric monitoring tools
is a solid strategy in the nanoscale world.
The Two Sides Of DFM:
Physical And Parametric
Process-based (physical) DFM technology
is concerned with identifying and correcting particle defects or process
variations that can lead to functional failures like shorts and opens.
Electrically-based DFM is concerned with parameters that fall out of
specification or adversely impact functional performance. The great
advantage to E-DFM (electrical DFM) is the directness of evaluating
the function and performance of an electrical device through electrical
measurements. In comparison, physical DFM can be indirect to the point
of being circuitous, using, for example, a visual observation to estimate
the electrical functionality of a component or element. Physical DFM
variables can easily reach into the hundreds and thousands, accounting
for the surge in test time and data volume as fabrication processes
push beyond 90 nm into 65 nm, 45 nm, and further. On the other hand,
variables or parameters for electrical DFM are so focused they literally
be counted on one hand.
Parametric Variables
& Die-Level Monitoring
There are four core electrical parameters:
Threshold Voltage, VTH
Resistance, R
Capacitance, C
Digital transition on-current,
ION
While this list could include power,
leakage current, and other variables, it is these four parameters that
are the most critical values needed to accurately predict yield. These core parameters are from on-chip test
structures designed with the capabilities required to validate transistor
and interconnect modeling, Process Design Kit (PDK) values, predicted
versus actual performance, and substantiate design closure with a high
degree of confidence.
Die-Level Monitoring & PDKChek®
The break-through in practical parametric
yield improvement lies in the use of specialized test structures located
in-situ. While simple in concept, the execution was only made possible
using patented nanoDFM™ technology pioneered and patented by Ridgetop
Group, Inc. Designing test structures for evaluating parametric yield
and, most importantly, analyzing critical patterns and parameters requires
extraordinary attention to details:
What are the test parameters
and patterns?
How are the measurements
conducted?
What test equipment?
How to minimize manual
interference?
How to design individual
tests that produce clear, unambiguous, accurate results and trends?
Beyond the test structures for monitoring,
testing, and reporting, a powerful analytical engine is needed as well
as a suite of other tools for assisting in accelerating the maturation
of a process / device through yield and performance optimization.
PDKChek® technology was created using an engineering
design philosophy that is customer-driven. Test structures and internal
elements are modularized for maximum customization. At the finest granularity,
each die has an instantiation of PDKChek®. The test structure is a self-contained IP
with internal test devices designed for producing the monitored electrical
values. These test devices are the target transistors, resistors, and
capacitors; they are exact matches for the devices in the host. Each
PDKChek® instance is created with the host circuitry
so every fabrication experience is identical for monitor and host. The
use of an interface like JTAG (IEEE-1149.1) makes data collection possible
at every stage of die handling and beyond. Since PDKChek®
can be turned on and off, failure analysis and operational data can
be extracted to support post-manufacturing activities. Wafer probing
is difficult at sub-90 nm. To prevent probe damage, Ridgetop's patented
buffered socket approach protects transistors from damage during the
easy and accurate measurement extraction process.
PDKChek® technology is designed for verification of
the PDKs supplied by foundries. The interplay of foundries, fabless
designers, and pure-play manufacturers has created communication issues
when clear channels are needed more than ever. Since foundry PDKs do
not reliably model all parameters fabless designers need, Ridgetop developed
the technology needed determine key parameters like transistor matching.
Figure 2: PDKChek®
Feedback Diagram
Ridgetop Group's PDKChek®
allows designers to compare the performance between different foundries
using the same independent die-level monitor. The die-level process
monitors provide critical mismatch performance comparison by fabless
IC firms. PDKChek® provides the accurate modeling data needed
to realize the full potential of advanced semiconductor processes. This
improves model predictability, which reduces the need for chip respins.
Transistor Matching
Transistor matching is an example
of a yield-limiting parametric variation that PDKChek® monitors and detects. Many circuit applications
are based on component pairs that are assumed to be identical. These
matched pairs are very common. For example, transistor pairs are used
in Digital-to-Analog Converter (DAC), Analog-to-Digital Converter (ADC),
Phased-Locked Loop (PLL), amplifier, operational amplifier, comparator,
and voltage reference circuits. Transistor mismatches represent the
extreme technical challenge of defect isolation taken to the individual
transistor-level. The technical competency requirement is so great,
ITRS singled out single transistor defect identification as a challenge
in its 2007 Technology Roadmap. But the challenge is warranted since
transistor mismatching results in yield loss, performance/precision
reduction, and redesign time/resources.
NanoDFM™, Sentinel PHMPro™,
And Other Ridgetop Innovations
Ridgetop Group's solution, PDKChek®,
is part of the nanoDFM™ tool suite and works with Sentinel PHMPro™,
a prognostic analysis engine. The nanoDFM™ suite includes AdaptChek™ (Adaptive Biasing IP core), PDKChek®
(Foundry PDK verification for fabless designers), QualChek™
(Process calibration for foundries), TestChek™ (IC test time reduction), and YieldChek™
(Process-aware DFM monitor). Each tool shares the unique and patented
nanoDFM™ technology designed to monitor parametric
variations. On-chip test structures replicate multiple transistor types
and capture threshold voltage, polysheet resistance, capacitance, and
ION to address parametric variations from design and manufacturing
interactions and provide the precise, real-time data required for accurate
physical modeling by TCAD. With the introduction of the nanoDFM™
tools such as PDKChek®, designers have the ability to analyze and
address process variations at the design stage without changing their
existing design flow.
Ridgetop Group is a privately-held
firm founded in 2000 to provide advanced tools and IP for critical systems.
With an excellence in engineering innovation motto, Ridgetop has gained
an impressive customer list, including NASA, Honeywell, DARPA, NAVAIR,
Raytheon Missile Systems, Daimler AG, ATK/Mission Research, General
Dynamics, US Department of Energy, Air Force Research Labs, and other
government and commercial firms in North America, Europe, and Asia.
Ken Harris is the senior technical writer at Ridgetop Group. An expert in usability and cross-cultural communication, he has served as plenary speaker and symposium chair for advanced topics in technical communication and information design. Over a 25-year career, he has become an award-winning writer, designer, and illustrator with awards ranging from academic contests to juried national and international competitions. He received a BA in English from the University of New Mexico, graduating cum laude and with departmental honors. He has taught graduate-level technical writing and graphic design at Georgia Tech and Southern Polytechnic State University and is a senior fellow in the Society for Technical Communication.
