Once upon a time the only people that
cared about design methodology were CTO's. Only people at this level
of a corporation had the luxury to think about ethereal topics like
engineering productivity and the quality levels of design. Engineers
had chips to complete and deadlines to worry about. Managers had to
get it done on schedule and budget. It was practical to "just get
it done", by whatever was the fastest and cheapest means.
For the last 10 years, the fastest and
cheapest means has been to utilize low-cost, off-shore resources to
keep the pace. It is a brute force method, and like all brute force
methods tends to be a short-term solution to an endemic problem. Sooner
or later the laws of supply and demand kicks in as skilled resources
become scarce and want more money. Throwing bodies at a problem might
make sense for a time but offers only temporary relief and at some point
becomes impractical.
In an analysis of 55,000 chip plans, ChipEstimate.com showed that IP represented
56% of the total area of chips designed in 2007 and is increasing steadily
year over year. If we accept that IP reuse is clearly one of the best
approaches for improving chip design efficiency, then we must ask ourselves
the next question: How can we increase the efficiency of designing IP?
One must first think about the design
of IP as being different than normal design. The requirements are different
and more complex, and distinct in a number of ways:
An IP design must have the
proper interfaces and function to be useful in multiple chips
An IP design must be able
to be integrated by someone other than the original designer
An IP design must be able
to be maintained by someone other the original designer
Failing to meet these fundamental requirements,
a design is simply not IP, and therefore not capable of achieving the
full productivity and quality benefits of true IP. The bar is high,
and many semiconductor companies struggle with the challenge of creating
true IP for internal reuse, while dealing with the realities of getting
the chips out on schedule and under budget.
NXP has long been a thought leader in
the area of IP reuse and an active participant in IP-oriented standards
organizations like the Spirit
Consortium. About 10 years
ago, NXP (then Philips Semiconductor) realized that to differentiate
itself from its competitors it not only needed to lower costs, but also
improve its efficiency and speed to bring quality products to market.
Their visionary CTO at the time, Theo Classen, challenged the design
organization to harness the collective intelligence of the company to
find a way to design a complex chip in a single month. The result of
this vision was an enterprise level initiative, CoReUse, which defined a complete design methodology
for designing chips under the paradigm that all design was considered
IP and capable of being reused at some point in the future.
The challenges with creating reusable
IP extend far beyond coding guidelines and best practices, but require
deep considerations into:
System level design and modeling
required for higher levels of integration
Architectural level partitioning
to allow maximum modularity and inter-IP connectivity
Test and debug strategies
that are portable to the chip level
Reusable verification environments
that can be tasked not only for IP design but for IP integration
Understanding what kind of
documentation is necessary to preserve the original designer knowledge
and intent such that the IP can live long into the future
How to manage such a methodology
so that it can remain flexible and improve and grow over time to stay
current with latest industry standards and EDA tool flows
These are all essential elements for
any company hoping to consistently build high quality reusable IP. Most
commercial IP companies have mastered the design of IP as a matter of
survival in its business. Many semiconductor companies (which are many
orders magnitude larger and more complex) have struggled with how to
achieve this across their entire enterprise. Such a transition is just
a matter of time as the winners and losers in SoC-based design will
increasingly be decided by how well the company makes the transition
to higher levels of efficiency enabled by IP-based design.
NXP is working with IPextreme to make
the proven CoReUse methodology available to all semiconductor and
systems companies, allowing companies new to IP reuse to set up enterprise-wide
reuse methodologies leveraging the experience of NXP. Isaac Newton famously
said, "If I have seen a little further it is by standing on the shoulders
of Giants." Advances in IP reuse, like advances in all science involve
building on the successful work of others.
Prior to founding IPextreme, Mr. Savage
created and ran the Star IP Program at Synopsys, where he provided an
IP brokering function for major semiconductor companies. Prior to that,
Mr. Savage was head of the Synopsys DesignWare engineering organization,
where he introduced many design practices and quality measures, which
eventually became part of the Reuse Methodology Manual, a seminal book
on Intellectual Property design. From 1982-1995 he worked for Tandem
Computers, and there developed an interest in advanced design methodologies
around high reliability design. Mr. Savage began his career at Fairchild
Semiconductor developing semiconductor test equipment. Mr. Savage is
a well-known and published authority in the field of semiconductor intellectual
property. Mr. Savage has a BS in Computer Engineering from Santa Clara
University and an MBA from Pepperdine University.
