With off-chip memory access
being one of the major contributors to chip power dissipation, designers
are turning to embedded non-volatile memory (NVM) for a variety of mobile
and other power-sensitive applications. Over the past few years,
a chip's power consumption has increasingly become a prime chip performance
specification. As a result, the need for low power embedded memory has
become critical in many designs.
Sidense recently introduced
a Low Power OTP memory architecture that can be used in many NVM areas
where one-time or several-time in-the-field programmability is needed.
While OTP bit-cell design determines the minimum power needed to read
a memory cell, equally important are many other design factors that
go into the arrays of bit-cells that comprise the memory macros that
ultimately find their way onto a chip. This paper will outline
an antifuse OTP bit-cell, based on Sidense's 1T-Fuse™ technology
and describe some of the low-power design techniques used to develop
the SLP family of memory IP.
1T-Fuse Bit Cell
All Sidense high-density and
low-power OTP antifuse arrays (SiPROM and SLP) are based on the same
1T-Fuse structure shown in Figure 1. The split channel,
two-terminal, one-transistor cell comprises both thin and thick oxide
regions under a single polysilicon gate. In its un-programmed
state, the thin-gate oxide region is an open circuit forming an MOS
capacitor between the gate and the channel induced in the substrate.
When a high enough voltage is applied to the gate, the thin gate oxide
breaks down, forming a permanent link between the word line and the
channel, representing a programmed state.
Figure 1.
The small size of the single-transistor 1T-Fuse OTP bit-cell minimizes
read power consumption.
Since the Sidense bit-cell
is a single transistor device, its area is much smaller than any other
field-programmable Logic NVM, whether antifuse-based 1.5T one-time programmable
(OTP) or floating-gate multi-time programmable (MTP) memories.
The small bit-cell size results in a smaller memory array footprint,
which in turn reduces bit-line and word-line pre-charge and switching
power consumption.
However, even more significant
power saving results from the way the bit-cells are designed into the
OTP array.
Low-Power
OTP Array Design
When designing any circuit
to minimize active power, the two keys are to use minimum area devices
and to put them as close as possible to minimize parasitic interconnect
capacitance. This is no different for any memory array, including
the SLP macros.
As discussed in the prior section,
the 1T-Fuse OTP arrays are inherently lower power because of a smaller
footprint. Sidense SLP macros are designed using minimum size transistors
as much as possible, thus minimizing the interconnect capacitance and
the total capacitance switched during a clock cycle.
In addition, a unique hierarchical
bit-line architecture with reduced bit-line swing and a power optimized
decoding scheme are used to further minimize array switching power.
Current sensing is not an option
for low power systems, as it requires a DC current through the cell
and through a reference. Sidense SLP macros use a low-power charge-sensing
scheme where all the charge leaking through the cells is collected to
create a voltage signal for the sense amplifier. This method is possible
because of the very consistent programmed state characteristics of the
split-channel cell.
Designing your sense amplifiers
not to consume any DC power is also a must. The SLP macros use a cross-coupled
latch type of sense amplifier that doesn't turn on until there is
sufficient voltage on an input to be correctly read. Once you turn a
sense amp on, positive feedback drives it to one of two zero-current
states. Everything else in the design follows simple static CMOS logic
so there is no DC current (other than leakage).
Yet another important technique
for reducing average power consumption in the OTP array is to minimize
the number of unnecessary switching and precharge operations. This is
achieved on the system level by optimizing the address switching sequence.
Optimized Power Supply
Along with the core VDD
supply voltage, the SLP macros require two additional voltage levels:
VPP for programming and VRR for read. The programming
voltage VPP can be supplied either from an external pin or
from a charge pump. VRR sets the active word line voltage
level and is required during a read operation to determine the state
of a memory cell, either programmed or un-programmed.
Sidense offers a stand-alone
Integrated Power Supply (IPS) Module that generates all the necessary
voltage levels from the standard IO voltage supply. This arrangement
allows the user to optimize the overall power supply scheme.
Figure 2.
This block diagram shows the connections
between an SLP memory macrocell and
the optional IPS (Integrated Power Supply)
module, containing a VRR regulator and VPP
charge pump.
SLP Power Dissipation
The active power level of an
SLP macro is very low. Typical read power for a 256 Kbit macro
is Ptotal = 5µW/MHz + 0.4µW/MHz/IObit. Typical standby
currents are just a few tens of nanoamps for a 256-Kbit array.
When designing a system, remember
that the power dissipation of the memory array is very dependent on
how the addresses switch when accessing the array during a read operation.
There is opportunity to minimize this power by optimizing the address
space allocation and keeping the address bus as quiet as possible.
Jim Lipman joined Sidense as Director
of Marketing early in 2008. Prior to Sidense, Jim worked at Cain Communications
as Vice President of Client Services, TechOnLine as Content Director,
and at EDN Magazine as ASIC and EDA Editor. He also was employed by
VLSI Technology, where he held various training, marketing and public
relations positions, and has done chip designs at both Hewlett-Packard
and Texas Instruments.
Jim received
his BSEE and MSEE degrees from Carnegie-Mellon University in Pittsburgh
and his Doctorate in Electrical Engineering from Southern Methodist
University in Dallas. He also has a Masters of Business Administration
from Golden Gate University in San Francisco. Jim is a senior member
of the IEEE.
Acknowledgements
I would like to thank Armin
Bluschke, Rick Phillips and Wlodek Kurjanowicz for their technical assistance
and for reviewing this paper.
